As the focus in microelectronics is gradually changing to include more emphasis on packaging, added values may be attained in packages by using System-in-Packages (SiP) methods. SiP methods may be considered as the leading viable solution for the ongoing trend in function integration. SiP methods include placing several dies into one package, either side-by-side or on top of each other. However, the miniaturization trend may, more or less, reduce the use of dies side-by-side. Therefore, additional approaches may enhance the trend to minimize die real estate, while providing high speed and reliable interfaces.